1. Technical Field
The invention disclosed broadly relates to transistor circuits and more particularly relates to transistor driver circuits for buses.
2. Background Art
When driving wire-or buses, bus settling time has a major influence on system performance. It is impossible to terminate these buses by classical methods due to varying line lengths and varying impedance of modules connected to the bus. Other methods to decrease bus settling time must be used.
A typical bus structure is illustrated in FIG. 1. In this bus configuration, from two to 32 modules may be connected. Any combination of modules may be drivers and/or receivers. The driver/receiver relationship will change on a cycle-by-cycle basis to include the range from one driver and 31 receivers to 32 drivers. A module uses its drive output as its receiver input, since any particular module does not know if it is the only driver active for that particular cycle.
The existing method of attempting to properly terminate such a bus is to terminate each end of the bus with resistors which are equal to the loaded bus impedance of the bus. The loaded impedance of the bus is defined as: EQU ZL=ZO*SQRT(CO*SL/(CO*SL+CIN*#DROPS)) (1)
where:
ZO is the characteristic impedance of the transmission line, PA1 CO is the per unit length capacitance of the transmission line, PA1 CIN is the equivalent capacitance of each drop on the bus, PA1 SL is the total line length of the bus (excluding stubs) PA1 and #DROPS is the total number of modules connected to the bus PA1 VDL is the down level of the driver, PA1 RT is the termination resistor value and PA1 VBB is the resistor termination voltage.
While this is a fair approximation if each bus drop presents only an invariant capacitance load, examination of FIG. 1 indicates that in the real world this is a coarse approximation at best. As modules go from driver/receiver to receiver only, the impedance at each bus drop changes rapidly. In addition, each bus drop has inductance associated with the input connector and power supply pins. Finally each bus drop has a length of transmission line from the module pin to the driver/receiver and each driver/receiver has inductance and capacitance associated with its own package. As system speeds go up, none of these effects are negligible.
In the practical case equation 1 gives an initial estimate of the correct end termination resistors and either experimental results or computer simulation is used to home in on the best value.
The drivers on this type of bus have to be similar to the normal open collector/drain driver. They must be capable of sinking all the current from both end termination resistors when the driver is the only one active. They must also be able to operate when multiple drivers are active at either driver output polarity. This requirement dictates unidirectional drive capability only, since if the drivers were bidirectional, any driver sinking current would have to sink all the up level drive capability of every other driver on the bus. Bidirectional drivers can be used on buses. This function is provided by tristate drivers. The use of tristate drivers requires a bus architecture which does not allow multiple drivers of different output polarity to be on concurrently. This requirement is not met in many architectures, such as those requiring multiple drop driver enables.
Consider the bus structure in FIG. 1 with a single driver on. The current this driver sinks is 2*(VBB-VDL)/RT.
where:
When this driver attempts to turn off, the voltage wave created at the input to the transmission line on the driver module is 2*(VBB-VDL)*ZO/RT where ZO is the transmission line characteristic impedance. This voltage wave can have large amplitude if the ratio ZO/RT is large. This is usually the case with practical values of transmission line and termination resistors. The large voltage wave reflects as it encounters the various stubs and main line segments and creates severe ringing on the bus which elongates the bus settling time (the time at which all receivers on the bus can distinguish between a 1 and a 0). The apparently obvious but incorrect fix would be to increase RT. While this will certainly decrease the bus ringing it also increases the bus low-to-high transition time. In the prior art practice described above, this trade between bus ringing and bus rise time is exactly what is evaluated either experimentally o by computer simulation.